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SM5158A Serial Input PLL Frequency Synthesizer

OVERVIEW
The SM5158A is a serial data programma-ble PLL Frequency Synthesizer LSI fabricated in NPC's proprietary Molybdenum-gate CMOS technology.
Ratios of reference frequency divider and input frequency divider can be independently set.

FEATURES
- Up to 200MHz input frequency (VDD=4.5V)
- Up to 35MHz reference frequency (VDD=4.5V)
- 5 to 65535 programmable reference frequency divider ratio
- 1056 to 65535 programmable input frequency divider ratio
- Lock detector
- Either Active or Passive filter can be externally used.
- 16-pin plastic DIP and 16-pin S-SOP

PinNameDescription
1XITo connect external crystal and capacitor, or external clock input pin.
2XOTo connect external crystal and capacitor,or oscilator output signal can be available at this pin.
3FVBuffered input frequency divider output. Phase detector input
4VCCPositive supply pin. Apply +2.7 to 5.5 Volts.
5DOPCharge pump output for passive lowpass filter. Single ended tristate output.
6GNDGround
7LDLock detector output. Logic Low when PLL is unlocked.
8FINComparison frequency input.Internal feedback resistor for AC coupling. Input frequency range 20MHz to 200MHz.
9CLShift register clock input.
10DataSerial data input.
11ENLatch enable input.
12DOAChrage pump output for active lowpass filter. Single ended tristate output.
13FRBuffered reference frequency devider output. Phase detector input.
14TestTest pin. Left open.
15OVBuffered phase detector output to a differential lowpass filter.
16ORBuffered phase detector output to a differential lowpass filter.

Phase Loced Loop Software


Similar Packages


Serial Data Input Timing
Serial Data Input Timing
tsu1 = 80nS
tsu2 = 80nS
tH = 80nS

Divider Data setting procedure
Serial Data to Reference and Frequency Divider

Input data must be MSB first. Final bit(17th bit) is assigned to the control bit.
Data are written into shift register at the rising edge of the CLK signal. When LE is HIGH,data is transferred from the shift register to either the latch of reference divider or input divider. Thus data must be written on the shift register while LE is remaining LOW.
While all bits of the N latch to are "0", the N counter will be disabled, DOA, DOP are floating, and the supply current will be decreased.
While all bits of the R latch are "0", oscilltor will be disabled. While all bits of R and N latches are "0", supply current decreases to 10uA or less.

16 BIT Data for R or N latch
16 BIT DATA FOR R or N latch


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