PLL0305A Serial Input PLL Frequency Synthesizer
Overview
PLL0305A is a PLL syntheseizer where input frequency divider ratio can be set by external inputting serial data. The reference frequency divider ratio can be selected from 8 choices stored in a built-in ROM.
Features
30MHz F
in
15MHz F
osc
Reference frequency divider ratios from 16 to 8192
Input frequency divider ratios from 5 to 16383
Lock detector pin
Can be used active or passive filters
Pin
Name
Description
1
RA 1
WIN
Transceiver
2
RA 2
WIN
Transceiver
3
øV
Output for differential LowPassFilter
4
øR
Output for differential LowPassFilter
5
Vcc
4,5Volt to 5,5Volt
6
PD
P
Passive filter
7
GND
WIN
Transceiver
8
LD
Loop Detect - Unlocked = Low and Locked = High
9
F in
Frequency input
10
CLOCK
WIN
Transceiver
11
DATA
Serial data input
12
ENABLE
WIN
Transceiver
13
PD
A
Active filter
14
TEST
Factory test
15
REF out
Reference frequency out
16
X out
X-tal output
17
X in
X-tal input
18
RA 0
WIN
Transceiver
Phase Loced Loop Software
RA2
RA1
RA0
Divider ratio
0
0
0
16
0
0
1
512
0
1
0
1024
0
1
1
2048
1
0
0
3668
1
0
1
4096
1
1
0
6144
1
1
1
8192
WIN
Transceiver
t
su1
= 300nS
WIN
Transceiver
t
su2
= 300nS
WIN
Transceiver
t
H
= 300nS
Input frequency divider data setting
Input data MSB first.
Data is input on the rising edge of CLOCK.
While the ENABLE signal is "H", data is transferred from shift register to input frequency divider.
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