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PLL0305A Serial Input PLL Frequency Synthesizer


Overview
PLL0305A is a PLL syntheseizer where input frequency divider ratio can be set by external inputting serial data. The reference frequency divider ratio can be selected from 8 choices stored in a built-in ROM.

Features
30MHz Fin
15MHz Fosc
Reference frequency divider ratios from 16 to 8192
Input frequency divider ratios from 5 to 16383
Lock detector pin
Can be used active or passive filters

PinNameDescription
1RA 1WINTransceiver
2RA 2WINTransceiver
3ÝVOutput for differential LowPassFilter
4ÝROutput for differential LowPassFilter
5Vcc4,5Volt to 5,5Volt
6PDPPassive filter
7GNDWINTransceiver
8LDLoop Detect - Unlocked = Low and Locked = High
9F inFrequency input
10CLOCKWINTransceiver
11DATASerial data input
12ENABLEWINTransceiver
13PDAActive filter
14TESTFactory test
15REF outReference frequency out
16X outX-tal output
17X inX-tal input
18RA 0WINTransceiver

Phase Loced Loop Software


RA2RA1RA0Divider ratio
00016
001512
0101024
0112048
1003668
1014096
1106144
1118192

Timing Diagram
WINTransceiver tsu1 = 300nS
WINTransceiver tsu2 = 300nS
WINTransceiver tH = 300nS


Input frequency divider data setting
Input data MSB first.
Data is input on the rising edge of CLOCK.
While the ENABLE signal is "H", data is transferred from shift register to input frequency divider.
Data setting




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