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MB15A01 PLL Frequency Synthesizer


MB15A01 PIN-Description

DESCRIPTION
The MB15A01 is a serial-input PLL (phase locked loop) frequency synthesizer LSI supporting a pulse swallow system.
The LSI consists of: a 1.1 GHz band, dual-modulus prescaler allowing either of 64/65 and 128/129 frequency divisions to be selected, a control signal generator circuit, a 19-bit shift register, a 15-bit latch, a reference divider (binary 14-bit reference counter), a 1-bit switch counter, a phase comparator with phase conversion functions, a charge pump, a crystal oscillator, an 18-bit latch, and programmable dividers (binary 7-bit swallow counter and binary 11-bit pro-grammable counter).
The LSI is housed in a 16-pin or 20-pin SSOP package, contributing to space saving of the system incorporating it.
In addition, the MB15A01 operates at a low supply voltage of 3.0 V (typical), achieving low current consumption (typically ICC = 6.5 mA)
MB15A01 Bolck Diagram

FEATURES
&127; Operation at high speed: fin = 1.1 GHz (Vin = –10 dBm)
&127; Pulse swallow function: Internal dual-modulus prescaler allowing either of 64/65 and 128/129 frequency divisions to be selected
&127; Low current consumption: ICC = 6.5 mA (typical)
&127; Serial-input 18-bit programmable divider
- Divide ratio of binary 7-bit swallow counter (0 to 127)
- Binary 11-bit programmable counter (16 to 2,047)
&127; Serial-input 15-bit reference divider
- Divide ratio of binary 14-bit programmable reference counter (6 to 16,383)
- 1-bit switch counter (for setting the prescaler divide ratio)
&127; Serial data configuration compatible with conventional models such as MB1511
&127; Two different phase comparator outputs
- Internal charge pump output (bipolar type)
- Output for external charge pump
&127; Wide range of operating temperature: Ta = –40 to +85C

PinNameDescription
1OSCINCrystal oscillator connection pin serving as a reference divider input pin (Oscillator circuit input pin)
2OSCOUTCrystal oscillator connection pin (Oscillator circuit output pin)
3VPPower supply pin for charge pump output. Connect this pin to VCC when the internal charge pump is not used.
4VCCPower supply pin
5DOInternal charge pump output pin
6GNDGND pin
7LDLock detector output pin. When locked: LD = “H”, When unlocked: LD = “L”
8fINPrescaler input pin. The pin must be AC-coupled for input.
9ClockClock input pin for 19-bit and 16-bit shift registers. The shift resistors reads data at the rise of the clock pulse.
10DataBinary-coded serial data input pin. The last bit in the data is a control bit.
Control bit = “H”: Sends data to the 15-bit latch.
Control bit = “L”: Sends data to the 18-bit latch.
11LELoad enable signal input pin (with pull-up resistor). When LE = “H”, the pin sends the contents of the shift register to the latch according to the control bit.
12FCPhase comparator phase switching pin (with pull-up resistor). When FC = “L”, the pin inverts characteristics of the phase comparator. It also switches the fout pin (test pin) output between fr and fp.
13NCNo Connection
14fOUTPhase comparator input monitor pin. The pin outputs the reference divider output (fr) or programmable divider output (fp) signal depending on the FC pin input level. It is an N channel open-drain output.
15PPhase comparator output pin for external charge pump. This pin is an N channel open-drain output.
16RPhase comparator output pin for external charge pump. This pin is a CMOS output.

Similar Packages


FUNCTIONAL DESCRIPTIONS
Pulse Swallow Function
For the pulse swallow function, use the following equations to select their respective setting values:
fVCO = ((P x N) + A) x fOSC / R
fVCO : Output frequency of externally connected VCO
P : Prescaler divide ratio (64 or 128)
N : Divide ratio of 11-bit programmable counter (16 to 2047)
A : Divide ratio of 7-bit swallow counter (0 to 127, A fOSC : Reference oscillation frequency
R : Divide ratio of 14-bit programmable reference counter (6 to 16383)

Serial Data Input Method
Serial data is processed using three input pins (Data, Clock, and LE pins) to control the 15-bit reference divider and the 18-bit programmable divider separately.
Input binary-coded serial data to the Data pin.
Serial data is input to the internal shift register in sequence at the rise of each clock pulse. When the load enable signal input pin has a high level (or open), the input data is transferred to the latch depending on the control bit.
Control bit = “H”: Transfer to the 15-bit latch
Control bit = “L”: Transfer to the 18-bit latch

Serial Data Input Timing
Serial Data Input Timing

Divide Ratio of Reference Divider
The reference divider consists of a 16-bit shift register, a 15-bit latch, and a 14-bit reference counter. Serial data is made up of the following 16 bits:
Serial Data to Reference Divider

Divide Ratio of Programmable Divider
The programmable divider consists of a 19-bit shift register, an 18-bit latch, 7-bit swallow counter, and an 11-bit programmable counter. Serial data is made up of the following 19 bits:
Serial Data to Programmable Divider


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