PLL - Phase Locked LoopsAn introduction to Phase Locked Loops
Phase-Locked Loop (PLL) circuits are used for frequency control. Figure 1 contains a block diagram of a basic PLL. The circuit operation is typical of all phase-locked loops. It is basically a feedback system that controls the phase of a voltage-controlled oscillator (VCO).
The input signal is applied to one phase detector input. The other input is connected to a divide-by-N counter output. Normally the frequencies of both signals will be nearly the same. The phase detector output is a voltage proportional to the phase difference between the two inputs. This signal is applied to the loop filter. The loop filter determines the PLL's dynamic characteristics. The filtered signal controls the VCO. Note that the VCO output is at a frequency that is N times the input supplied to the frequency reference input. This output signal is sent back to the phase detector via the divide-by-N counter.
Normally, the loop filter is designed to match the characteristics required by the PLL's application. If the PLL is to acquire and track a signal, the loop filter bandwidth will be greater than if it expects a fixed-input frequency. The frequency range which the PLL will accept and lock on is called the capture range. Once the PLL is locked and tracking a signal, the range of frequencies the PLL will follow is called the tracking range. Generally, the tracking range is larger than the capture range. The loop filter also determines how fast the signal frequency can change and still maintain lock. This is the maximum slewing rate. The narrower the loop filter bandwidth, the smaller the achievable phase error. This comes at the expense of slower response and reduced capture range.
Parallel Programmable PLL-circuits
Figure 2Figure 2 shows a typical 9-bit parallel probramming PLL-circuits.
The Reference Divider is often a preprogrammed divider witch divided by 1024, and the Divide-By-N counter can be set from 21 - 1 to 2N - 1 where N is number of programming inputs.
If the X-tal is 10.240000Hz, the refrerence frequency will be:
10,240000MHz / 1024 = 10kHz
an if the Programmable Divider is set to 29 - 1 (512 - 1 = 511) the VCO-frequency will be:
10kHz x 511 = 5,11MHz.
Serial Programmable PLL-circuits
PLL-circuits for high frequencies is often use a a Dual Modular Prescaler to divide down the VCO-freuency, and the Divide-By-N counter can consist of both a Swallow Counter and a Programmable Counter.
Figure 3 shows a typical serial programmable PLL-circuit. Both Reference Divider and the Swallow Counter/Programmable Counter can be programmed.
The most common serial input is a 3-wire connection (e.g. Motorola) or 2-wire (e.g. Phillips).
Take a loock at sites Phase Locked Loops Programmer for PLL-software.
AN-335: Digital PLL Synthesis
AN-885: Introduction to Single Chip Microwave PLL's
AN-1000: A Fast Locking Scheme for PLL Frequency Synrhesizers
AN-1001: An Analysis and Performance Evaluation of a Passive Filter Design Technique for Charge Pump PLL's