SM5158A Serial Input PLL Frequency Synthesizer

OVERVIEW
The SM5158A is a serial data programma-ble PLL Frequency Synthesizer LSI fabricated in NPC's proprietary Molybdenum-gate CMOS technology.
Ratios of reference frequency divider and input frequency divider can be independently set.

FEATURES
- Up to 200MHz input frequency (VDD=4.5V)
- Up to 35MHz reference frequency (VDD=4.5V)
- 5 to 65535 programmable reference frequency divider ratio
- 1056 to 65535 programmable input frequency divider ratio
- Lock detector
- Either Active or Passive filter can be externally used.
- 16-pin plastic DIP and 16-pin S-SOP

Pin	Name	Description
1	X_I	To connect external crystal and capacitor, or external clock input pin.
2	X_O	To connect external crystal and capacitor,or oscilator output signal can be available at this pin.
3	F_V	Buffered input frequency divider output. Phase detector input
4	V_CC	Positive supply pin. Apply +2.7 to 5.5 Volts.
5	D_OP	Charge pump output for passive lowpass filter. Single ended tristate output.
6	GND	Ground
7	LD	Lock detector output. Logic Low when PLL is unlocked.
8	F_IN	Comparison frequency input.Internal feedback resistor for AC coupling. Input frequency range 20MHz to 200MHz.
9	CL	Shift register clock input.
10	Data	Serial data input.
11	EN	Latch enable input.
12	D_OA	Chrage pump output for active lowpass filter. Single ended tristate output.
13	F_R	Buffered reference frequency devider output. Phase detector input.
14	Test	Test pin. Left open.
15	O_V	Buffered phase detector output to a differential lowpass filter.
16	O_R	Buffered phase detector output to a differential lowpass filter.

Phase Loced Loop Software

Similar Packages

Serial Data Input Timing

t_su1 = 80nS
t_su2 = 80nS
t_H = 80nS

Divider Data setting procedure
Serial Data to Reference and Frequency Divider

Input data must be MSB first. Final bit(17th bit) is assigned to the control bit.
Data are written into shift register at the rising edge of the CLK signal. When LE is HIGH,data is transferred from the shift register to either the latch of reference divider or input divider. Thus data must be written on the shift register while LE is remaining LOW.
While all bits of the N latch to are "0", the N counter will be disabled, D_OA, D_OP are floating, and the supply current will be decreased.
While all bits of the R latch are "0", oscilltor will be disabled. While all bits of R and N latches are "0", supply current decreases to 10uA or less.

16 BIT Data for R or N latch

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