PLL 2001
Serial Input PLL Frequency Synthesizer

Pin Connection
The PLL2001P and PLL2001S is a serial data programmable PLL Frequency Syntheseizer.
Ratios of reference frequency divider and input frequency divider can be independently set.
Block Diagram

- Up to 200MHz input frequency (VDD=4.5V)
- Up to 20MHz reference frequency (VDD=4.5V)
- 5 to 65535 programmable reference frequency divider ratio
- 272 to 65535 programmable input frequency divider ratio
- FV and FR output terminals
- Lock detector
- Either Active or Passive filter can be externally used.

1RITo connect external crystal and capacitor, or external clock input pin.
2ROTo connect external crystal and capacitor,or oscilator output signal can be available at this pin.
3FVBuffered input frequency divider output. Phase detector input
4VCCPositive supply pin. Apply +2.7 to 5.5 Volts.
5DOPCharge pump output for passive lowpass filter. Single ended tristate output.
7LDLock detector output. Logic Low when PLL is unlocked.
8FINComparison frequency input. Internal feedback resistor for AC coupling.
9CLShift register clock input.
10DataSerial data input.
11ENLatch enable input.
12DOAChrage pump output for active lowpass filter. Single ended tristate output.
13FRBuffered reference frequency devider output. Phase detector input.
14RangeHIGH: FIN is 5MHz to 250MHz 1,0VP-P
LOW: FIN is DC to 22MHz 1,5VP-P
15OVBuffered phase detector output to a differential lowpass filter.
16ORBuffered phase detector output to a differential lowpass filter.

Phase Loced Loop Software

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Serial data input timing

Serial data input timing
tsu1 = 300nS
tsu2 = 300nS
tH = 300nS

Divider data setting procedure

Divider data setting procedure
Input data must be MSB first. Final bit (17th bit) is assigned to the control bit.
Data are written into shift register at the rising edge of the CLK signal.
When LE is HIGH, data is transferred from the shift register to either the latch of reference divider or input divider. Thus data must be written on the shift register while LE is remaining L0W.

While all bits of the N latch to are "0", the N counter will be disabled, DOA, DOP are floating, and the supply current will be decreased.

While all bits of the R latch are "0", oscillator will be disabled.
While all bits of R and N latches are "0" and both N and R counters will be disabled, and the supply current decreases to 10uA or less.
Shift register clock input

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