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NJ88C28 FREQUENCY SYNTHESISER
WITH NON-RESETTABLE COUNTERS


The NJ88C28 is a synthesiser circuit fabricated on the GPS CMOS process and is capable of achieving high sideband attenuation and low noise performance. It contains a reference oscillator, 11-bit programmable reference divider, digital and sample-and-hold comparators, 10-bit programmable ‘M’ counter, 7-bit programmable ‘A’ counter and the necessary control and latch circuitry for accepting and latching the input data.
Data is presented serially under external control from a suitable microprocessor. Although 28 bits of data are initially required to program all counters, subsequent updating can be abbreviated to 17 bits, when only the ‘A’ and ‘M’ counters require changing.
The NJ88C28 is intended to be used in conjunction with a two-modulus prescaler such as the SP8715 series to produce a universal binary coded synthesiser for up to 1100MHz operation.
FEATURES
- Low Power Consumption
- High Performance Sample and Hold Phase Detector
- Serial Input with Fast Update Feature
- 5V Operation
- Fast Lock Up Time
- SSOP Package Option

PinNameDescription
1PDAAnalog output from the sample and hold phase comparator for use as a ‘fine’ error signal.
Output at (VDD 2VSS)/2 when the system is in lock.
Voltage increases as fv phase lead increases; voltage decreases as fr phase lead increases.
Output is linear over only a narrow phase window, determined by gain (programmed by RB).
2PDBThree-state output from the phase/frequency detector for use as a ‘coarse’ error signal.
fv > fr or fv leading: positive pulses with respect to the bias point VBIAS
fv r or fr leading: negative pulses with respect to the bias point VBIAS
fv = fr and phase error within PDA window: high impedance.
3FVThis pin is an open drain output from the ‘M’ counter.
4LDAn open-drain lock detect output at low level when phase error is within PDA window (in lock); high impedance at all other times.
5FINThe input to the main counters, normally driven from a prescaler, which may be AC-coupled or, when a full logic swing is available, may be DC-coupled.
6VSSNegative supply (ground).
7VDDPositive supply.
8BAND 0Latch outputs, providing an output of the data from the ‘B’ register.
9

10		OSCIN

OSCOUT		These pins form an on-chip reference oscillator when a series resonant crystal is connected across them. Capacitors of appropriate value are also required between each end of the crystal and ground to provide the necessary additional phase shift. An external reference signal may, alternatively, be applied to OSCIN. This may be a low-level signal, AC-coupled, or if a full logic swing is available it may be DC-coupled. The program range of the reference counter is 3 to 2047, with the division ratio being twice the programmed number.
11BAND 1Latch outputs, providing an output of the data from the ‘B’ register.
12DATAInformation on this input is transferred to the internal data latches during the appropriate data read time slot. DATA is high for a ‘1’ and low for a ‘0’. There are three data words which control the NJ88C24; MSB is first in the order: ‘A’ (7 bits), ‘M’ (10 bits), ‘R’ (11 bits).
13CLOCKData is clocked on the negative transition of the CLOCK waveform. If less than 28 negative clock transitions have been received when the ENABLE line goes low (i.e., only ‘M’ and ‘A’ will have been clocked in), then the ‘R’ counter latch will remain unchanged and only ‘M’ and ‘A’ will be transferred from the input shift register to the counter latches. This will protect the ‘R’ counter from being corrupted by any glitches on the clock line after only ‘M’ and ‘A’ have been loaded If 28 negative transitions have been counted, then the ‘R’ counter will be loaded with the new data.
14ENABLEWhen ENABLE is low, the DATA and CLOCK inputs are disabled internally. As soon as ENABLE is high, the DATA and CLOCK inputs are enabled and data may be clocked into the device. The data is transferred from the input shift register to the counter latches on the negative transition of the ENABLE input and both inputs to the phase detector are synchronised to each other.
15CAPThis pin allows an external capacitor to be connected in parallel with the internal ramp capacitor and allows further programming of the device. (This capacitor is connected from CAP to VSS
16MCModulus control output for controlling an external dual-modulus prescaler. MC will be low at the beginning of a count cycle and will remain low until the ‘A’ counter completes its cycle. MC then goes high and remains high until the ‘M’ counter completes its cycle, at which point both ‘A’ and ‘M’ counters are reset. This gives a total division ratio of MP+ A, where P and P+1 represent the dual-modulus prescaler values. The program range of the ‘A’ counter is 0-127 and therefore can control prescalers with a division ratio up to and including ¸128/129. The programming range of the ‘M’ counter is 3-1023 but M > 8 or M = 8 for correct PDA operation and, for correct operation with a prescaler, M > A or M = A. Where every possible channel is required, the minimum total division ratio N should be: N > P2 - P or N = P2 - P, where N = MP+ A.
17RBAn external sample and hold phase comparator gain programming resistor should be connected between this pin and VSS.
18CHAn external hold capacitor should be connected between this pin and VSS




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