MB1503 PLL Frequency Synthesizer

The Fujitsu MB1503 is a serial input phase-locked loop (PLL) frequency synthesizer with a pulse-swallow function. A stand-by mode is provided to limit power consumption during intermittent operation.
The MB1503 is configured of a 1.1GHz dual-modulus prescaler with 128/129 divide ratio, control signal generator, 16-bit shift register, 15-bit latch, programmable reference divider (binary 14-bit programmable reference counter), 1-bit switch counter, phase comparator with phase conversion function, charge pump, crystal oscillator, 19-bit shift register, 18-bit latch, programmable divider (binary 7-bit swallow counter and binary 11-bit programmable counter), analog switches, and an intermittent operation control circuit that selects the operating or stand-by mode depending on the power-save control input state (PS).
The MB1503 operates from a single +5 V supply. Fujitsu’s advanced technology achieves an Icc of 8mA, typical. The stand-by mode current consumption is just 100mA.
Block Diagram
&127; High operating frequency : fIN = 1.1GHz (PIN = –10dBm)
&127; Pulse-swallow function : High-speed dual-modulus prescaler with 128/129 divide ratio
&127; Low supply current : ICC = 8mA typ. at 5V
&127; Power-saving stand-by mode : 100mA
&127; Serial input, 18-bit programmable divider consisting of:
– Binary 7-bit swallow counter : 0 to 127
– Binary 11-bit programmable counter : 16 to 2,047
&127; Serial input 15-bit programmable reference divider consisting of:
– Binary 15-bit programmable reference counter: 8 to 16,383
– 1-bit switch counter sets prescaler divide ratio
&127; On-chip analog switch for fast lock-up
&127; On-chip charge pump
&127; Wide operating temperature range: –40 to +85C

1OSCINCrystal oscillator connection pin serving as a reference divider input pin (Oscillator circuit input pin)
2OSCOUTCrystal oscillator connection pin (Oscillator circuit output pin)
3VPPower supply pin for charge pump output. Connect this pin to VCC when the internal charge pump is not used.
4VCCPower supply pin
5DOInternal charge pump output pin
7LDLock detector output pin. When locked: LD = “H”, When unlocked: LD = “L”
8fINPrescaler input pin. The pin must be AC-coupled for input.
9ClockClock input pin for 19-bit and 16-bit shift registers. The shift resistors reads data at the rise of the clock pulse.
10DataBinary-coded serial data input pin. The last bit in the data is a control bit.
Control bit = “H”: Sends data to the 15-bit latch.
Control bit = “L”: Sends data to the 18-bit latch.
11LELoad enable signal input pin (with pull-up resistor). When LE = “H”, the pin sends the contents of the shift register to the latch according to the control bit.
12FCPhase comparator phase switching pin (with pull-up resistor). When FC = “L”, the pin inverts characteristics of the phase comparator. It also switches the fout pin (test pin) output between fr and fp.
13BiSWAnalog switch output. BiSW is usually in the high-impedance state. When the switch is turned on (LE is high), the state of the internal charge pump is output.
14frMonitor pin of phase comparator input. It is the same as the programmable reference divider output.
15fpMonitor pin of phase comparator input. It is the same as the programmable divider output.
16PSPower save signal input.
Set PS low while the system is powered (never use pin 16 as it is opened)
PS = High : Operation mode
PS = Low : Stand-by mode

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Phase Loced Loop Software

Pulse Swallow Function
For the pulse swallow function, use the following equations to select their respective setting values:
fVCO = ((P x N) + A) x fOSC / R
fVCO : Output frequency of externally connected VCO
P : Prescaler divide ratio (64 or 128)
N : Divide ratio of 11-bit programmable counter (16 to 2047)
A : Divide ratio of 7-bit swallow counter (0 to 127, A fOSC : Reference oscillation frequency
R : Divide ratio of 14-bit programmable reference counter (6 to 16383)

Serial Data Input Method
Serial data is processed using three input pins (Data, Clock, and LE pins) to control the 15-bit reference divider and the 18-bit programmable divider separately.
Input binary-coded serial data to the Data pin.
Serial data is input to the internal shift register in sequence at the rise of each clock pulse. When the load enable signal input pin has a high level (or open), the input data is transferred to the latch depending on the control bit.
Control bit = “H”: Transfer to the 15-bit latch
Control bit = “L”: Transfer to the 18-bit latch

Serial Data Input Timing
Serial Data Input Timing

Divide Ratio of Reference Divider
The reference divider consists of a 16-bit shift register, a 15-bit latch, and a 14-bit reference counter. Serial data is made up of the following 16 bits:
Serial Data to Reference Divider

Divide Ratio of Programmable Divider
The programmable divider consists of a 19-bit shift register, an 18-bit latch, 7-bit swallow counter, and an 11-bit programmable counter. Serial data is made up of the following 19 bits:
Serial Data to Programmable Divider

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