MB1502 PLL Frequency Synthesizer

The Fujitsu MB1502, utilizing BI-CMOS technology, is a single chip serial input PLL synthesizer with pulse-swallow function.
The MB1502 contains a 1.1GHz two modulus prescaler that can select of either 64/65 or 128/129 divide ratio, control signal generator, 16-bit shift register, 15-bit latch, programmable reference divider (binary 14-bit programmable reference counter), 1-bit switch counter, phase comparator with phase conversion function, charge pump, crystal oscillator, 19-bit shift register, 18-bit latch, programmable divider (binary 7-bit swallow counter and binary 11-bit programmable counter) and analog switch to speed up lock up time.
It operates supply voltage of 5V typ. and achieves very low supply current of 8mA typ. realized through the use of Fujitsu Advanced Process Technology.
Block Diagram
&127; High operating frequency: fIN MAX =1.1GHz (VIN MIN =10dBm)
&127; Pulse swallow function: 64/65 or 128/129
&127; Low supply current: ICC =8mA typ.
&127; Serial input 18-bit programmable divider consisting of:
— Binary 7-bit swallow counter: 0 to 127
— Binary 11-bit programmable counter: 16 to 2047
&127; Serial input 15-bit programmable reference divider consisting of:
— Binary 14-bit programmable reference counter: 8 to 16383
— 1-bit switch counter (SW) sets divide ratio of prescaler
&127; On-chip analog switch achieves fast lock up time
&127; 2 types of phase detector output
— On-chip charge pump (Bipolar type)
— Output for external charge pump

1OSCINCrystal oscillator connection pin serving as a reference divider input pin (Oscillator circuit input pin)
2OSCOUTCrystal oscillator connection pin (Oscillator circuit output pin)
3VPPower supply pin for charge pump output. Connect this pin to VCC when the internal charge pump is not used.
4VCCPower supply pin
5DOInternal charge pump output pin
7LDLock detector output pin. When locked: LD = “H”, When unlocked: LD = “L”
8fINPrescaler input pin. The pin must be AC-coupled for input.
9ClockClock input pin for 19-bit and 16-bit shift registers. The shift resistors reads data at the rise of the clock pulse.
10DataBinary-coded serial data input pin. The last bit in the data is a control bit.
Control bit = “H”: Sends data to the 15-bit latch.
Control bit = “L”: Sends data to the 18-bit latch.
11LELoad enable signal input pin (with pull-up resistor). When LE = “H”, the pin sends the contents of the shift register to the latch according to the control bit.
12FCPhase comparator phase switching pin (with pull-up resistor). When FC = “L”, the pin inverts characteristics of the phase comparator. It also switches the fout pin (test pin) output between fr and fp.
13BISWAnalog switch output. Usually BISW pin is set high-impedance state. When internal analog switch is ON (LE pin is high level), this pin outputs internal charge pump state.
14fOUTMonitor pin of phase comparator input. fOUT pin outputs either programmable reference divider output (fr) or programmable divider output (fp) depending upon FC pin input level.
15PPhase comparator output pin for external charge pump. This pin is an N channel open-drain output.
16RPhase comparator output pin for external charge pump. This pin is a CMOS output.

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Pulse Swallow Function
For the pulse swallow function, use the following equations to select their respective setting values:
fVCO = ((P x N) + A) x fOSC / R
fVCO : Output frequency of externally connected VCO
P : Prescaler divide ratio (64 or 128)
N : Divide ratio of 11-bit programmable counter (16 to 2047)
A : Divide ratio of 7-bit swallow counter (0 to 127, A fOSC : Reference oscillation frequency
R : Divide ratio of 14-bit programmable reference counter (6 to 16383)

Serial Data Input Method
Serial data is processed using three input pins (Data, Clock, and LE pins) to control the 15-bit reference divider and the 18-bit programmable divider separately.
Input binary-coded serial data to the Data pin.
Serial data is input to the internal shift register in sequence at the rise of each clock pulse. When the load enable signal input pin has a high level (or open), the input data is transferred to the latch depending on the control bit.
Control bit = “H”: Transfer to the 15-bit latch
Control bit = “L”: Transfer to the 18-bit latch

Serial Data Input Timing
Serial Data Input Timing

Divide Ratio of Reference Divider
The reference divider consists of a 16-bit shift register, a 15-bit latch, and a 14-bit reference counter. Serial data is made up of the following 16 bits:
Serial Data to Reference Divider

Divide Ratio of Programmable Divider
The programmable divider consists of a 19-bit shift register, an 18-bit latch, 7-bit swallow counter, and an 11-bit programmable counter. Serial data is made up of the following 19 bits:
Serial Data to Programmable Divider

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