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PLL2002
Serial Input PLL Frequency Synthesizer

Pin Connection
DESCRIPTION
The PLL2002A is a serial data programmable PLL Frequency Syntheseizer. Ratios of reference frequency divider and input frequency divider can be independently set.
Pin Connection

FEATURES
- Up to 550MHz input frequency (VDD=4.5V)
- Up to 20MHz reference frequency (VDD=4.5V)
- Up to 65535 programmable reference frequency divider ratio
- Up to 16777215 programmable input frequency divider ratio
- fV and fR output terminals
- Lock detector
- Either Active or Passive filter can be externally used.

PinNameDescription
1XINReference X-tal Oscillator Input
2XOUTReference X-tal Oscillator Output
3NCNo Connection
4VSSPositive Supply Voltage - 5 Volt
5PDPhase Detector Output - VCO Voltage Out
6GNDGround
7LDLoop Detector - Loop Detected=HIGH - Not Detected=LOW
8FINVCO Frequency In
9CLKClock from CPU
10DataData from CPU
11LELatch Enable from CPU
12NCNo Connection
13NCNo Connection
14RangeHIGH: FIN is High Frequency Range. LOW: FIN is Low Frequency Range
15fVPhase detector output to differential lowpass filter
16fRPhase detector output to differential lowpass filter

Phase Loced Loop Software


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Serial data input timing

Serial data input timing
tsu1 = 300nS
tsu2 = 300nS
tH = 300nS


Divider data setting procedure

Divider data setting procedure
Input data must be MSB first. Final bit is assigned to the control bit.
Data are written into shift register at the rising edge of the CLK signal.
When LE is HIGH, data is transferred from the shift register to either the latch of reference divider or input divider. Thus data must be written on the shift register while LE is remaining L0W.

While all bits of the N latch are "0", the N counter will be disabled.
While all bits of the R latch are "0", oscillator and R counter will be disabled.
While all bits of R and N latches are "0", both R and N counters will be disabled.
Shift register clock input
R packet is 16-bits MSB first hold the R Value, 1 Control Bit always signal that it is a R packet, then LE is toggled to complete this packet.

N packet is 24-bits, MSB first, the first 8 bits (In Range "LOW") are always low, the next 16 bits hold the N value, the a 0 control bit signals complete this packet.



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