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PLL03A
PLL08A
PLL Frequency Synthesizer

Overview

This 27 MHz band, PLL frequency synthesizer LSI chip is designed specifically for CB transceivers. The integrated circuit`s incorporates PLL circuitry and a controller for CB applications on a single CMOS chip.
This PLL-circuit use a 7 bit ROM programmable divide-by-N counter. The ROM-table is programmed from factory to 40 channels.
PinNameDescription
1VccPositive Supply Voltage
2RIReferency Oscillator Input
3LD1
4LD2
5LD3
6PDPhase Detector Output
7T/RTransmit=HIGH Receive=LOW
8F inVCO Frequency Input
9P6Programmable input 6
10P5Programmable input 5
11P4Programmable input 4
12P3Programmable input 3
13P2Programmable input 2
14P1Programmable input 1
15P1Programmable input 0
26GNDGround

Explanation of pin function terms


Programming Chart for
PLL03A (U.S. - AM)
PLL08A (EEC - FM)

ChannelRX
Divided by
TX
Divided by
112061297
212081299
..........
2212581349
..........
4012941385
NOTES:
1. Spesial divided by 2 circuit in TX mode change Referency Divider output to 2.5kHz steps.
2. 91-count upshifts on TX provides 455kHz offset for receiver IF mixing when VCO frequency is doubled.
3. Sinse chip cannot divide VCO directly, they are down-mixed with the 10.240MHz Referency Oscillator signal, produsing 6MHz outputs (RX Mode) and 3MHz outputs (TX Mode) into dividers. Standard 16MHz VCO is used.
4. PLL08A contains only the first 22 FCC channels for EEC use; otherwise both chip are identical.

Example of VCO Determination, Channel 1:
1206 x 5kHz + 10.240MHz = 16.270MHz (RX-Mode)
1297 x 2.5kHz + 10.240MHz = 13.4825MHz (TX-Mode)
(13.4825MHz x 2 = 26.965MHz)


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