|1||PDA||Analog output from the sample and hold phase comparator for use as a fine error signal.|
(VDD 2VSS)/2 when the system is in lock.
Voltage increases as fv phase lead increases; voltage
decreases as fr phase lead increases.
Output is linear over only a narrow phase window, determined
by gain (programmed by RB).
|2||PDB||Three-state output from the phase/frequency detector for use as a coarse error signal.|
fv > fr or fv leading: positive pulses with respect to the bias point VBIAS
fv r or fr leading: negative pulses with respect to the bias point VBIAS
fv = fr and phase error within PDA window: high impedance.
|3||LD||An open-drain lock detect output at low level when phase error is within PDA window (in lock); high
impedance at all other times.|
|4||FIN||The input to the main counters, normally driven from a prescaler, which may be AC-coupled or, when
a full logic swing is available, may be DC-coupled.|
|5||VSS||Negative supply (ground).|
|These pins form an on-chip reference oscillator when a series resonant crystal is connected across
them. Capacitors of appropriate value are also required between each end of the crystal and ground
to provide the necessary additional phase shift. An external reference signal may, alternatively, be
applied to OSCIN. This may be a low-level signal, AC-coupled, or if a full logic swing is available it may
be DC-coupled. The program range of the reference counter is 3 to 2047, with the division ratio being
twice the programmed number.
|9||D0||Data on these inputs is transferred to the internal data latches during the appropriate data read time
slot. D0 is LSB.|
|10||D1||Data on these inputs is transferred to the internal data latches during the appropriate data read time
|11||D2||Data on these inputs is transferred to the internal data latches during the appropriate data read time
|12||D3||Data on these inputs is transferred to the internal data latches during the appropriate data read time
slot. D3 is MSB.|
|14||PE||This pin is used as a strobe for the data. A logic 1 on this pin transfers data from the D0-D3 pins to
the internal latch addressed by the data select (DS0-DS2) pins . A logic 0 disables the data inputs.|
|15||DS0||Data select inputs for addressing the internal data latches|
|16||DS1||Data select inputs for addressing the internal data latches|
|17||DS2||Data select inputs for addressing the internal data latches|
|18||MC||Modulus control output for controlling an external dual-modulus prescaler. MC will be low at the beginning
of a count cycle and will remain low until the A counter completes its cycle. MC then goes high and
remains high until the M counter completes its cycle, at which point both A and M counters are reset.
This gives a total division ratio of MP+A, where P and P+1 represent the dual-modulus prescaler
values. The program range of the A counter is 0-127 and therefore can control prescalers with a
division ratio up to and including divided by 128/129. The programming range of the M counter is 8-1023
and, for correct operation, M>A or M=A. Where every possible channel is required, the minimum total division
ratio should be P2 - 2P.|
|19||RB||An external sample and hold phase comparator gain programming resistor should be connected
between this pin and VSS.|
|20||CH||An external hold capacitor should be connected between this pin and VSS|