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MC145159 PLL Integrated Circuits

Interfaces with Dual–Modulus Prescalers
&127; Operating Temperature Range: – 40 to 85C
&127; Low Power Consumption Through Use of CMOS Technology
&127; 3.0 to 9.0 V Supply Range
&127; On– or Off–Chip Reference Oscillator Operation
&127; Compatible with the Serial Peripheral Interface (SPI) on CMOS MCUs
&127; R Range = 3 to 16383
&127; N Range = 16 to 1023, A Range = 0 to 127
&127; High–Gain Analog Phase Detector

The MC145159–1 has a programmable 14–bit reference counter, as well as fully programmable divide–by–N/divide–by–A counters. The counters are programmed serially through a common data input and latched into the appropriate counter latch, according to the last data bit (control bit) entered. When combined with a loop filter and VCO, this device can provide all the remaining functions for a PLL frequency synthesizer operating up to the device’s frequency limit. For higher VCO frequency operations, a down mixer or a dual–modulus prescaler can be used between the VCO and the PLL.

Phase Loced Loop Software

Similar Packages


Oscillator Input and Oscillator Output (PDIP, SOG – Pins 2, 3; SSOP – Pins 7, 8)
These pins form an on–chip reference oscillator when connected to terminals of an external parallel–resonant crystal. Frequency–setting capacitors of appropriate value must be connected from OSC in to V SS and OSC out to V SS . OSC in may also serve as input for an externally–gen-erated reference signal. This signal will typically be ac coupled to OSC in , but for larger amplitude signals (standard CMOS logic levels), dc coupling may also be used. In the external reference mode, no connection is required to OSC out .

Frequency Input (PDIP, SOG – Pin 10, SSOP – Pin 15)
Input to the positive edge triggered divide–by–N and di-vide– by–A counters. f in is typically derived from a dual– modulus prescaler and is ac coupled. This input has an inverter biased in the linear region to allow use with ac coupled signals as low as 500 mV peak–to–peak or direct coupled signals swinging from V DD to V SS .

Serial Data Input (PDIP, SOG – Pin 12, SSOP – Pin 17)
Counter and control information is shifted into this input. The last data bit entered goes into the one–bit control shift register. A logic 1 allows the reference counter information to be loaded into its 14–bit latch when ENB goes high. A logic 0 entered as the control bit disables the reference counter latch. The divide–by–A/divide–by–N counter latch is loaded, regardless of the contents of the control register, when ENB goes high.

Transparent Latch Enable (PDIP, SOG – Pin 13, SSOP – Pin 18)
A logic high on this input allows data to be entered into the divide–by–A/divide–by–N latch and, if the control bit is high, into the reference counter latch. Counter programming is unaffected when ENB is low. ENB should be kept normally low and pulsed high to transfer data to the latches.

Shift Register Clock (PDIP, SOG – Pin 11, SSOP – Pin 16)
A low–to–high transition on this input shifts data from the serial data input into the shift registers.

Ramp Capacitor (PDIP, SOG – Pin 15, SSOP – Pin 20)
The capacitor connected from this pin to V SS 4 is charged linearly, at a rate determined by R R . The voltage on this capacitor is proportional to the phase difference of the frequencies present at the internal phase detector inputs. A polystyrene or mylar capacitor is recommended.

Ramp Current Bias Resistor (PDIP, SOG – Pin 20, SSOP – Pin 5)
A resistor connected from this pin to V SS 4 determines the rate at which the ramp capacitor is charged, thereby affecting the phase detector gain.

Hold Capacitor (PDIP, SOG – Pin 18, SSOP – Pin 3)
The charge stored on the ramp capacitor is transferred to the capacitor connected from this pin to either V DD 4 or V SS 4. The ratio of C R to C H should be large enough to have no effect on the phase detector gain (C R > 10 C H ). A low–leak-age capacitor should be used.

Output Bias Current Resistor (PDIP, SOG – Pin 1, SSOP – Pin 6)
A resistor connected from this pin to V SS 4 biases the output N–Channel transistor, thereby setting a current sink on the analog phase detector output. This resistor adjusts the APD out bias current.

Analog Phase Detector Output (PDIP, SOG – Pin 17, SSOP – Pin 2)
This output produces a voltage that controls an external VCO. The voltage range of this output (V DD = + 9 V) is from below + 0.5 V to + 8 V or more. The source impedance of this output is the equivalent of a source follower with an exter-nally variable source resistor. The source resistor depends upon the output bias current controlled by the output bias current resistor, R O . The bias current is adjustable from 0.01 mA to 0.5 mA. The output voltage is not more than 1.05 V below the sampled point on the ramp. With a constant sample of the ramp voltage at 9 V and the hold capacitor of 50 pF, the instantaneous output ripple is about 5 mV peak– to–peak.

Ramp Charge Indicator (PDIP, SOG – Pin 4, SSOP – Pin 9)
This output is high from the time f R goes high to the time f V goes high (f R and f V are the frequencies at the phase detector inputs). This high voltage indicates that the ramp capacitor, C R , is being charged.

Three–State Frequency Steering Output (PDIP, SOG – Pin 6, SSOP – Pin 11)
If the counted down input frequency on f in is higher than the counted down reference frequency of OSC in , this output goes low. If the counted down VCO frequency is lower than that of the counted down OSC in , this output goes high. The repetition rate of the frequency steering output pulses is approximately equal to the difference of the frequencies of the two counted down inputs from the VCO and OSC in .

Lock Detector Indicator (PDIP, SOG – Pin 9, SSOP – Pin 14)
This output is high during lock and goes low to indicate a non–lock condition. The frequency and duration of the non– lock pulses will be the same as either polarity of the fre-quency steering output.

Dual Modulus Prescaler Control (PDIP, SOG – Pin 8, SSOP – Pin 13)
The modulus control level is low at the beginning of a count cycle and remains low until the divide–by–A counter has counted down from its programmed value. At that time, the modulus control goes high and remains high until the di-vide– by–N counter has counted the rest of the way down from its programmed value (N – A additional counts since both divide–by–N and divide–by–A are counting down during the first portion of the cycle). Modulus control is then set back low, the counters preset to their respective programmed values, and the above sequence repeated. This provides for a total programmable divide value of N T = N
P + A, where P
and P + 1 represent the dual modulus prescaler divide values respectively for high and low modulus control levels, N is the number programmed into the divide–by–N counter, and A is the number programmed into the divide–by–A counter.

Shift Register Output (PDIP, SOG – Pin 14, SSOP – Pin 19)
This pin is the non–inverted output of the last stage of the 32–bit serial data shift register. It is not latched by the ENB line. If unused, SR out should be floated.

Positive Power Supply (PDIP, SOG – Pin 5, SSOP – Pin 10) Positive power supply input for all sections of the device except the analog phase detector. V DD and V DD 4 should be powered up at the same time to avoid damage to the MC145159–1. V DD must be tied to the same potential as V DD 4.

Negative Power Supply (PDIP, SOG – Pin 7, SSOP – Pin 12) Circuit ground for all sections of the MC145159–1 except the analog phase detector. V SS must be tied to the same po-tential as V SS 4.

Analog Phase Detector Circuit Ground (PDIP, SOG – Pin 16, SSOP – Pin 1)
Separate power supply and ground inputs are provided to help reduce the effects in the analog section of noise coming from the digital sections of this device and the surrounding circuitry.

Analog Power Supply (PDIP, SOG – Pin 19, SSOP – Pin 4)
Separate power supply and ground inputs are provided to help reduce the effects in the analog section of noise coming from the digital sections of this device and the surrounding circuitry.

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