MC145157 PLL Integrated Circuits
The MC145157–2 has a fully programmable 14–bit reference counter, as well as a fully programmable ÷ N counter. The counters are programmed serially through a common data input and latched into the appropriate counter latch, according to the last data bit (control bit) entered.
The MC145157–2 is an improved–performance drop–in replacement for the MC145157–1. Power consumption has decreased and ESD and latch–up performance have improved.
&127; Operating Temperature Range: – 40 to 85°C
&127; Low Power Consumption Through Use of CMOS Technology
&127; 3.0 to 9.0 V Supply Range
&127; Fully Programmable Reference and ÷ N Counters
&127;÷ R Range = 3 to 16383
&127;÷ N Range = 3 to 16383
&127; f V and f R Outputs
&127; Lock Detect Signal
&127; Compatible with the Serial Peripheral Interface (SPI) on CMOS MCUs
&127; “Linearized” Digital Phase Detector
&127; Single–Ended (Three–State) or Double–Ended Phase Detector Outputs
&127; Chip Complexity: 6504 FETs or 1626 Equivalent Gates
Phase Loced Loop Software
Similar Packages
PIN DESCRIPTIONS
Frequency Input (Pin 8)
Input frequency from VCO output. A rising edge signal on this input decrements the ÷ N counter. This input has an inverter biased in the linear region to allow use with ac coupled signals as low as 500 mV p–p. For larger amplitude signals (standard CMOS logic levels), dc coupling may be used.
Shift Clock, Serial Data Inputs (Pins 9, 10)
Each low–to–high transition of the clock shifts one bit of data into the on–chip shift registers. The last data bit entered determines which counter storage latch is activated; a logic 1 selects the reference counter latch and a logic 0 selects the ÷ N counter latch.
Latch Enable Input (Pin 11)
A logic high on this pin latches the data from the shift regis-ter into the reference divider or ÷ N latches depending on the control bit. The reference divider latches are activated if the control bit is at a logic high and the ÷ N latches are activated if the control bit is at a logic low. A logic low on this pin allows the user to change the data in the shift registers without affecting the counters. ENB is normally low and is pulsed high to transfer data to the latches.
Reference Oscillator Input/Output (Pins 1, 2)
These pins form an on–chip reference oscillator when con-nected to terminals of an external parallel resonant crystal. Frequency setting capacitors of appropriate value must be connected from OSC in to ground and OSC out to ground. OSC in may also serve as the input for an externally–gener-ated reference signal. This signal is typically ac coupled to OSC in , but for larger amplitude signals (standard CMOS logic levels) dc coupling may also be used. In the external reference mode, no connection is required to OSC out .
Single–Ended Phase Detector A Output (Pin 5)
This single–ended (three–state) phase detector output produces a loop–error signal that is used with a loop filter to control a VCO.
Frequency f V > f R or f V Leading: Negative Pulses
Frequency f V
Frequency f V = f R and Phase Coincidence: High–Impedance State
Double–Ended Phase Detector B Outputs (Pins 16, 15)
These outputs can be combined externally for a loop–error signal. A single–ended output is also available for this pur-pose (see PD out ).
If frequency f V is greater than f R or if the phase of f V is leading, then error information is provided by fV pulsing low. fR remains essentially high.
If the frequency f V is less than f R or if the phase of f V is lagging, then error information is provided by fR pulsing low. fV remains essentially high.
If the frequency of f V = f R and both are in phase, then both fV and fR remain high except for a small minimum time period when both pulse low in phase.
R Counter Output, N Counter Output (Pins 13, 3)
Buffered, divided reference and f in frequency outputs. The f R and f V outputs are connected internally to the ÷ R and ÷ N counter outputs respectively, allowing the counters to be used independently, as well as monitoring the phase detector inputs.
Lock Detector Output (Pin 7)
This output is essentially at a high level when the loop is locked (f R , f V of same phase and frequency), and pulses low when loop is out of lock.
Buffered Reference Oscillator Output (Pin 14)
This output can be used as a second local oscillator, refer-ence oscillator to another frequency synthesizer, or as the system clock to a microprocessor controller.
Shift Register Output (Pin 12)
This output can be connected to an external shift register to provide band switching, control information, and counter programming code checking.
Positive Power Supply (Pin 4)
The positive power supply potential. This pin may range from + 3 to + 9 V with respect to V
SS
.
Negative Power Supply (Pin 6)
The most negative supply potential. This pin is usually ground.
Serial Data Input Method
Serial data is processed using three input pins (Data, Clock, and LE pins) to control the 15-bit reference divider and the 18-bit programmable divider separately.
Input binary-coded serial data to the Data pin.
Serial data is input to the internal shift register in sequence at the rise of each clock pulse. When the load enable signal input pin has a high level (or open), the input data is transferred to the latch depending on the control bit.
Control bit = “H”: Transfer to the 14-bit Reference Counter
Control bit = “L”: Transfer to the 14-bit Frequency Counter
Serial Data Input Timing
Divide Ratio of Reference Divider
The reference divider consists of a 14-bit shift register, a 14-bit latch, and a 14-bit reference counter. Serial data is made up of the following 15 bits:
Divide Ratio of Programmable Divider
The programmable divider consists of a 14-bit shift register, an 14-bit latch, 7-bit swallow counter, and an 11-bit programmable counter. Serial data is made up of the following 19 bits:
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