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LMX1501A PLL Frequency Synthesizer

1.1 GHz Frequency Synthesizer for RF Personal Communications

General Description
The LMX1501A are high performance frequency synthesizers with integrated prescalers designed for RF operation up to 1.1 GHz. They are fabricated using National's ABiC IV BiCMOS process.
The LMX1501A and the LMX1511 contain dual modulus prescalers which can select either a 64/65 or a 128/129 divide ratio at input frequencies of up to 1.1 GHz. Using a proprietary digital phase locked loop technique, the LMX1501A's linear phase detector characteristics can generate very stable, low noise local oscillator signals. Serial data is transferred into the LMX1501A via a three line MICROWIRE TM interface (Data, Enable, Clock). Supply voltage can range from 2.7V to 5.5V. The LMX1501A feature very low current consumption, typically 6 mA at 3V.
The LMX1501A is available in a JEDEC 16-pin surface mount plastic package.
&127; RF operation up to 1.1 GHz
&127; 2.7V to 5.5V operation
&127; Low current consumption: ICCe 6 mA (typ) at VCCe 3V
&127; Dual modulus prescaler: 64/65 or 128/129
&127; Internal balanced, low leakage charge pump
&127; Small-outline, plastic, surface mount JEDEC, 0.150Świde, package

&127; Cellular telephone systems (AMPS, NMT, ETACS)
&127; Portable wireless communications (PCS/PCN, Cordless)
&127; Advanced cordless telephone systems (CT-1/CT-1a, CT-2, ISM902-928)
&127; Other wireless communication systems

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Functional Description
The simplified block diagram below shows the 19-bit data register, the 14-bit R Counter and the S Latch, and the 18-bit N Counter (intermediate latches are not shown). The data stream is clocked (on the rising edge) into the DATA input, MSB first. If the Control Bit (last bit input) is HIGH, the DATA is transferred into the R Counter (programmable reference divider) and the S Latch (prescaler select: 64/65 or 128/129). If the Control Bit (LSB) is LOW, the DATA is transferred into the N Counter (programmable divider).

Serial Data Input Timing
Serial Data Input Timing
Notes: Parenthesis data indicates programmable reference divider data. Data shifted into register on clock rising edge. Data is shifted in MSB first.
Test Conditions: The Serial Data Input Timing is tested using a symmetrical waveform around V CC /2. The test waveform has an edge rate of 0.6 V/ns with amplitudes of 2.2V @ V CC e 2.7V and 2.6V @ V CC e 5.5V.

Divide Ratio of Reference Divider
Serial Data to Reference Divider
If the Control Bit (last bit shifted into the Data Register) is HIGH, data is transferred from the 19-bit shift register into a 14-bit latch (which sets the 14-bit R Counter) and the 1-bit S Latch (S15, which sets the prescaler: 64/65 or 128/129).

Divide Ratio of Programmable Divider
Serial Data to Programmable Divider
The N counter consists of the 7-bit swallow counter (A counter) and the 11-bit programmable counter (B counter). If the Control Bit (last bit shifted into the Data Register) is LOW, data is transferred from the 19-bit shift register into a 7-bit latch (which sets the 7-bit Swallow (A) Counter) and an 11-bit latch (which sets the 11-bit programmable (B) Counter).

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